Exemplary embodiments of the present invention relate to a semiconductor device and a fabrication method thereof, and more particularly, to a vertical channel type non-volatile memory device and a fabrication method thereof.
A non-volatile memory device maintains data stored therein although a power supply is cut off. As the current technology is reaching its limits in improving the integration degree of a memory device having a two-dimensional structure where a memory device is fabricated in a single layer over a silicon substrate, a non-volatile memory device having a three-dimensional structure where memory cells are stacked vertically over a silicon substrate is being developed.
Hereafter, a method for fabricating a typical non-volatile memory device having a three-dimensional structure and problems thereof will be described in detail with reference to the accompanying drawings.
FIG. 1 is a cross-sectional view illustrating a structure of a conventional vertical channel type non-volatile memory device.
Referring to FIG. 1, a lower selection transistor LST, a plurality of memory cells MC and an upper selection transistor UST are sequentially formed over a substrate 10 with a source region S formed therein.
First, a plurality of interlayer dielectric layers 11 and a plurality of conductive layers 12 for a gate electrode are formed over a substrate with a source region S formed therein, and trenches TRENCH exposing the surface of the substrate 10 are formed by etching the plurality of the interlayer dielectric layers 11 and the plurality of the conductive layers 12 for a gate electrode. Subsequently, a gate insulation layer 13 is formed on the internal wall of the trenches TRENCH. Subsequently, the trenches TRENCH are filled with a layer for a channel to thereby form channels CH. In this way, the lower selection transistor LST is formed.
Subsequently, a plurality of interlayer dielectric layers 11 and a plurality of conductive layers 12 for a gate electrode are formed over a substrate 10 with a lower selection transistor LST formed thereon, and trenches TRENCH exposing the surface of the channel of the lower selection transistor LST are formed by etching the plurality of the interlayer dielectric layers 11 and the plurality of the conductive layers 12 for a gate electrode. Subsequently, a charge blocking layer, a charge tapping layer, and a tunnel insulation layer (together labeled as “14”) are sequentially formed on the internal wall of the trenches. Herein, the charge trapping layer is used as a sort of a data storage for storing/erasing data by trapping/discharging charges. Generally, a nitride layer is used as the charge trapping layer. Subsequently, the trenches TRENCH are filled with a layer for a channel to thereby form channels CH. In this way, a plurality of memory cells MC are formed to be stacked along the channels protruded from the substrate 10.
Subsequently, a plurality of interlayer dielectric layers 11 and a plurality of conductive layers 12 for a gate electrode are formed over a substrate 10 with a plurality of memory cells MC formed thereon, and trenches TRENCH exposing the surface of the channel CH of the memory cell MC are formed by etching the plurality of the interlayer dielectric layers 11 and the plurality of the conductive layers 12 for a gate electrode. Subsequently, a gate insulation layer 13 is formed on the internal wall of the trenches TRENCH. Subsequently, the trenches TRENCH are filled with a layer for a channel to thereby form channels CH. In this way, the upper selection transistor UST is formed.
Herein, the plurality of the memory cells MC are coupled in series between the lower selection transistor LST and the upper selection transistor UST to thereby form a string ST and each of the channels CH is connected to a bit line BL.
According to the conventional technology described above, each of the memory cells MC may constitute a charge-trapping non-volatile memory device having a three-dimensional structure which includes a charge trapping layer for trapping charges. However, the charge-trapping non-volatile memory device has a drawback in that its characteristics are poorer than those of a floating gate type non-volatile memory device.
Specifically, the charge-trapping non-volatile memory device has a slower program/erase operation speed and poorer data retaining characteristics than the floating gate type non-volatile memory device. In particular, since the non-volatile memory device having a three-dimensional structure has the charge trapping layers of the plurality of the memory cells MC, which are stacked along the channels CH and are coupled with each other, the data retaining characteristics are deteriorated even more.
Therefore, in order to improve the performance of a memory device and raise reliability, it is required to develop a floating gate type non-volatile memory device that has a three-dimensional structure and a fabrication method thereof.